An integrated circuit memory, such as a static random access memory (SRAM), is generally implemented as an array of memory cells in a plurality of rows and columns. An array may be subdivided into blocks of memory cells. The memory cells are addressable through block, row, and column decoders for reading data from the memory cells or writing data into the memory cells. Each memory cell has a unique address at an intersection of a row and a column. The bit line pairs are commonly used for both reading data from, and writing data into, the memory cell. Typically, data is read from memory when a write enable signal is at a logic high (or inactive), and written into memory when the write enable signal is at a logic low, (or active). During a read cycle, a word line selects the addressed row of memory cells, and a pair of complementary bit lines communicate the data bit between the addressed row and a sense amplifier. The data exists as a relatively small differential voltag on the pair of complementary bit lines. A sense amplifier detects and amplifies the differential voltage and communicates it to the data output stage of the integrated circuit memory via read global data lines.
During a write cycle, a relatively large differential signal is provided on the bit lines in order to over-write the contents of a selected memory cell. At the end of a write cycle, the differential voltage remaining on the bit line pair must be reduced to a relatively low level so that the data is not erroneously written into a memory cell during the following read cycle. The differential voltage on the bit line pair must also be reduced quickly so that the read cycle is not unnecessarily extended. This process is called write recovery, or bit line equalization. Bit line equalization causes the voltages on the bit line pair to be close enough so that data is not overwritten and that the correct data is sensed quickly during the read cycle. Write recovery of the bit line pairs is embodied in a timing specification known as TWHAX (write signal high to an address invalid). TWHAX is essentially the time interval between the beginning of a read cycle, and the change of the address to select a different location in the memory array. During that time, write recovery, or bit line equalization occurs to prevent data from being overwritten during the following read cycle. The time period for write recovery must be long enough to allow bit line equalization to occur, but not so long that the read cycle is unnecessarily delayed. A minimum time of zero is usually given as the TWHAX timing specification.
If an address changes before the write enable signal becomes a logic high, TWHAX is considered to be negative, and bit line equalization may not be complete before the word line changes, thus causing a data reliability problem. This problem is more severe if the address selects a new word line within the same block as the previous word line, because less time is needed for address changes when they are within a block. For guard banding purposes, the TWHAX specification must not only be met, but exceeded. It is desirable that the memory ignore address changes that occur a few nanoseconds before the write cycle to read cycle change, because the user may have difficulty ensuring that the address does not change before the write enable signal changes. These difficulties may arise from the user's own timing circuitry as well as printed circuit board layout problems.